1. Field of the Invention
This invention relates to a semiconductor integrated circuit including MOS transistors, and more particularly to an integrated circuit containing MOS transistors for a TEG (Test Element Group) formed for measuring the characteristic of a MOS transistor group of a preset circuit.
2. Description of the Related Art
Generally, when a MOS integrated circuit is manufactured, MOS transistors called a TEG for equivalently measuring the resistivity of a substrate and the characteristic of MOS transistors formed on the substrate and pads connected to the MOS transistors are formed on a wafer on which an integrated circuit chip will be formed in order to evaluate the process. The characteristics of MOS transistors obtained from a TEG is also used as data for a simulation.
Such a TEG is arranged in a boundary portion (oh the scribe line) between the chips or in an area between pads formed along the periphery of the chip. In either case, the conventional TEG transistor is formed in an area formed at a relatively far distance from an area in which a MOS transistor group for circuit construction is formed.
Since the transistors in the MOS transistor group for circuit construction are generally formed at a high density and the TEG transistors are formed at a low density, the dimensions of the above two types of transistors are made different because of the process conditions.
That is, when a pattern of elements such as transistors is formed on the semiconductor substrate, light incident on the photoresist on one surface of the wafer spreads into the semiconductor substrate while it collides against organic molecules and is scattered in a forward direction. Part of the light entering the substrate is reflected, scattered in a backward direction as secondary photons and fed back into the photoresist. Thus, the photoresist is exposed to the light and the thickness of the resist pattern is reduced, and transistors whose pattern is determined by the resist pattern are formed with dimensions different from the desired dimensions.
Thus, since the dimensions of the transistors for circuit construction formed at a high density and the dimensions of the TEG transistors formed at a low density are different from each other, it becomes difficult to correctly evaluate the characteristics of the transistors for circuit construction by measuring the characteristics of the TEG transistors.
Further, if the TEG transistor is formed on the scribe line, the TEG transistor is destroyed when the chip area is cut apart from the wafer and separated. Therefore, when the characteristics of the transistors is evaluated after the chips are assembled, characteristic measurement by the TEG becomes impossible and it becomes impossible to obtain measurement data of the TEG transistors provided in one-to-one correspondence to the chips for the respective chips.
Thus, the TEG transistors formed in the conventional semiconductor integrated circuit have dimensions different from those of the transistors of the MOS transistor group for circuit construction, and it is difficult to correctly evaluate the characteristic of the transistors for circuit construction by measuring the characteristic of the TEG transistors.
Further, if the conventional TEG MOS transistor is formed on the scribe line of the semiconductor wafer, there occurs a problem that characteristic measurements cannot be made at the time of evaluation after assembling the chips, and measurement data of the TEG transistors provided in one-to-one correspondence to the respective chips cannot be obtained.